1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device having a semiconductor chip mounted therein.
2. Description of Related Art
As electronic devices are reduced in weight, thickness, and size, semiconductor devices tend to be produced in a miniaturized form. Packages of semiconductor devices have been increasingly reduced in size and weight, and the packages have become more compact.
FIGS. 10A to 10C are diagrams each showing a related art example of a semiconductor device having a small package. FIG. 10A is a plan view showing the semiconductor device of the related art example. FIG. 10B is a side view of the semiconductor device of FIG. 10A viewed from an X-direction, and FIG. 10C is a side view thereof viewed from a Y-direction. In FIGS. 10A to 10C, the semiconductor device of the related art example includes a semiconductor chip (not shown) that is encapsulated in a package 100. The package 100 has a substantially quadrangular prism shape. On two short side surfaces of the package 100, which face each other, there are provided flat leads 101 serving as terminals. The flat leads 101 are each connected to the semiconductor chip in the package 100 and each protrude in the X-direction from each of the side surfaces of the package 100. The semiconductor device of the related art example shown in FIGS. 10A to 10C is called 2-pin XSOF (Extremely thin Small Outline Flat lead).
The 2-pin XSOF is manufactured by a manufacturing method similar to that for a typical semiconductor device, as described below. First, a plurality of semiconductor chips formed on a semiconductor wafer are separated by cutting into individual pieces, and then, each of the individual semiconductor chips is electrically connected to the flat leads 101. Next, each of the individual semiconductor chips connected to the flat leads 101 is set in a mold and is molded with a resin. In this manner, the semiconductor chip and the flat leads 101 are encapsulated in each package.
As described above, conventional semiconductor devices are manufactured by carrying out an operation for individually connecting semiconductor chips to the flat leads 101. Meanwhile, Japanese Unexamined Patent Application Publication No. 2005-51130 discloses a method of manufacturing a semiconductor device by connecting semiconductor chips in a collective manner. FIG. 11 is a cross-sectional diagram showing an example of a semiconductor device having a small package as disclosed in Japanese Unexamined Patent Application Publication No. 2005-51130. In FIG. 11, a first MOS chip MC1 and a second MOS chip MC2 are planarly arranged on a lower electrode L1.
A drain electrode D1 of the MOS chip MC1 and a drain electrode D2 of the MOS chip MC2 are each directly connected to the lower electrode L1 to thereby form a common external drain electrode TD. Further, a gate electrode G1 of the MOS chip MC1 and a gate electrode G2 of the MOS chip MC2 are each directly connected to an upper electrode L2, whereby a first external gate electrode TG1 and a second external gate electrode TG2 are formed. Furthermore, source electrodes S1 and S2 (not shown) of the MOS chips MC1 and MC2 are each directly connected to the upper electrode L2, whereby first and second external source electrodes TS1 and TS2 (not shown) are formed. A resin R is filled between the upper electrode L1 and the lower electrode L2 to thereby form a leadless package LLP.
The semiconductor device as disclosed in Japanese Unexamined Patent Application Publication No. 2005-51130 is manufactured in the following manner. A plurality of MOS chips formed on a semiconductor wafer are separated by cutting into individual pieces, and then, the MOS chips MC1 and MC2 are mounted on a lead frame plate serving as the lower electrode L2. After that, with a gold bump formed on each of the MOS chips MC1 and MC2, a lead frame plate serving as the upper electrode L1 is connected to each of the MOS chips MC1 and MC2. The resin R is supplied between the upper electrode L1 and the lower electrode L2 and is molded, and the resultant is then separated by cutting into individual packages. In this manner, in the technique as disclosed in Japanese Unexamined Patent Application Publication No. 2005-51130, the upper electrode L2 is connected to the MOS chips in a collective manner, thereby reducing the number of manufacturing steps.
Incidentally, electrodes of semiconductor devices are generally subjected to outer plating in order to improve adhesion between each electrode and a solder. As disclosed in Japanese Unexamined Patent Application Publication No. 2005-51130, when a semiconductor device is formed such that a plurality of semiconductor chips are connected to lead frame plates in a collective manner and the plurality of semiconductor chips are separated by cutting into individual packages, the plating is generally performed prior to the separation by cutting. This is because, if the plating is performed prior to the separating by cutting, the plating can be applied to each lead frame plate. After the plating, the plurality of semiconductor chips are separated by cutting into individual packages, and a characteristic inspection is carried out to screen defective products (characteristic screening). However, the characteristic screening is performed on each of the individual packages separated by cutting. In other words, the characteristic inspection for screening defective products is performed on each package, which requires much time and labor.